'VIHAAN' on the VEGA Processor: India's Chip Design Comes of Age — An NDA Science & Technology Explainer

On 15 August 2026, the Ministry of Electronics & IT announced that Aheesa Digital Innovations, a Design Linked Incentive (DLI)-backed startup headquartered in Chennai, had achieved first-pass silicon success with 'VIHAAN' — a networking System-on-Chip (SoC) purpose-built for fibre broadband, designed around the indigenous VEGA microprocessor.

The dates are a nice touch of engineering theatre: the chip was taped out on Republic Day and achieved first-pass silicon success on Independence Day of the same year. It now proceeds towards production tape-out, targeted for 2027.

This is an excellent NDA science topic — a real Indian technological achievement resting on physics and electronics the General Ability paper tests, wrapped in a strategic story about self-reliance.

What actually happened, in plain terms

Three technical phrases carry the whole story, and each is worth knowing precisely:

• Tape-out — the moment a chip's completed design is sent to the foundry for manufacture. (The name survives from the era when the final design was delivered on magnetic tape.) It is the point of no return: masks are made, and a mistake now costs months and crores.
• First-pass silicon success — the manufactured chip works as intended on the very first attempt, with no redesign-and-refabricate cycle. This is the hard part. Most designs need one or more re-spins; achieving first-pass success is a genuine mark of design maturity, verification discipline and team competence.
• System-on-Chip (SoC) — a single chip integrating a processor core, memory, input-output interfaces and specialised accelerators that would earlier have been separate components on a circuit board.

VIHAAN is aimed at bringing fibre broadband to Indian homes. As India expands optical fibre, 5G and broadband-led services, the networking silicon inside every router and optical network terminal is currently imported almost entirely — which is exactly the gap this chip addresses.

The physics underneath — the part the exam tests

A semiconductor is a material whose electrical conductivity lies between that of a conductor and an insulator — silicon and germanium being the classic examples. What makes semiconductors extraordinary is that this conductivity can be controlled:

• Doping — deliberately adding impurities. Adding a pentavalent element (phosphorus, arsenic) donates free electrons and produces n-type material; adding a trivalent element (boron, gallium) creates holes and produces p-type.
• The p-n junction — joining the two produces a device that conducts in one direction and blocks the other: the diode.
• The transistor — a sandwich of doped regions in which a small voltage or current at one terminal controls a much larger current between the other two. That is switching and amplification, and it is the basis of all digital logic. A modern SoC contains billions of transistors.
• Temperature behaviour — unlike metals, the conductivity of a semiconductor increases with temperature, because thermal energy promotes more electrons across the band gap. That contrast between conductors and semiconductors is one of the most repeated one-line questions in this chapter, and it belongs with the notes on current electricity.

Node size — the "12nm" figures mentioned for other Indian chips in the release — refers to the manufacturing process generation. Smaller nodes pack more transistors into the same area, switch faster and consume less power per operation. The historical trend of transistor counts roughly doubling every two years is known as Moore's Law — an empirical observation, not a law of physics, and one that is slowing as devices approach atomic dimensions.

The three business models — and why "fabless" matters

Why the distinction matters strategically: a fabrication plant costs billions of dollars and takes years to build, whereas a design house needs talent, tools and capital of a far smaller order. India's realistic entry point was therefore design, where it already had a deep engineering talent base — a large share of the world's chip design engineering has been done in India for years, though mostly for foreign companies. The shift now being attempted is from doing design work for others to owning Indian products and intellectual property.

The release quantifies why design matters: chip design contributes up to 50% of the overall value addition in the semiconductor value chain and accounts for roughly 15–35% of the Bill of Materials cost of electronic products.

VEGA, RISC-V and why an ISA is strategic

VIHAAN is built on the indigenous VEGA microprocessor, developed by C-DAC under the Digital India RISC-V (DIR-V) programme. Alongside it, IIT Madras's SHAKTI family is the other major indigenous processor line.

The reason this matters requires one more concept. An Instruction Set Architecture (ISA) is the vocabulary of commands a processor understands — the contract between software and hardware. The dominant ISAs have historically been proprietary and licensed, meaning a country building processors on them pays royalties and depends on continued permission.

RISC-V is different: it is an open-source, royalty-free ISA. Anyone may design a processor implementing it without a licence or a licensor. For a country pursuing technological sovereignty, that is a strategically significant property — it removes a permission dependency at the most foundational layer of computing. This is why India's indigenous processor programmes are built on RISC-V rather than on a licensed alternative.

The policy architecture

The release sets out the ecosystem, and these figures are examinable:

• Design Linked Incentive (DLI) Scheme — supports Indian startups designing chips for satellite communications, drones, surveillance cameras, defence and aerospace systems, automotive, IoT, LED drivers, AI systems, telecom equipment and smart meters.
• State-of-the-art chip design tools made available to 455 organisations, including 350 academic institutions and 105 startups.
• DLI-supported companies have achieved 35 design tape-outs across various foundries and raised more than US$100 million in venture capital.
• Chips to Startup (C2S) Programme — 245 chip designs taped out by 71 academic institutions, aimed at building the future workforce.
• Semicon 2.0 — approved in July 2026 with an outlay of ₹1,27,500 crore, to build a globally competitive semiconductor ecosystem across design, manufacturing, advanced packaging, equipment, materials, R&D and skilled manpower.
• Aheesa itself raised about ₹40 crore from the Tamil Nadu Infrastructure Fund Management Corporation (TNIFMC) through the Tamil Nadu Emerging Sector Seed Fund and other private investors.

Other recent successes named in the release, which together show an ecosystem rather than a single result: Vervesemi Microelectronics (first-pass silicon on a BLDC motor controller using an indigenous processor from Incore Semiconductor), Netrasemi (12nm Vision SoC with video analytics acceleration), OptoML (12nm compute-in-memory SoC for faster, power-efficient AI), Mindgrove Technologies (Vision SoC for CCTV surveillance with PRAMA India) and IndieSemiC (global certification for a Bluetooth BLE 6 module).

In his Independence Day address the same day, the Prime Minister noted that three semiconductor plants have already been initiated and that another five to eight are expected over the coming seven to eight years, framing chips as indispensable to electronics, medical equipment and transport alike — "the entire world could come to a standstill without chips."

Why chips are a strategic commodity

Worth stating explicitly, because it is the heart of any lecturette on this subject:

• Everything runs on them. Phones, cars, medical equipment, power grids, missiles, satellites and payment systems all depend on semiconductors.
• Supply is extraordinarily concentrated. A small number of firms and geographies dominate advanced fabrication, and much of that capacity sits in a politically sensitive region. A disruption there halts industries worldwide — as the shortages of recent years demonstrated when car factories stopped for want of cheap chips.
• Defence dependence is unacceptable. Military systems built on foreign silicon carry both supply risk and, potentially, trust risk regarding what is inside the chip.
• It is a talent-intensive industry. Which is why 350 academic institutions receiving design tools, and 245 tape-outs from 71 institutions, matter as much as any single product.

The revision hook: On 15 August 2026 MeitY announced that Aheesa Digital Innovations, a Chennai-headquartered fabless startup backed by the Design Linked Incentive scheme, achieved first-pass silicon success with VIHAAN, a networking System-on-Chip for fibre broadband built using the indigenous VEGA microprocessor, taped out on Republic Day with production tape-out targeted for 2027, having raised about ₹40 crore from TNIFMC and others; chip design contributes up to 50% of value addition in the semiconductor chain and 15–35% of the bill of materials of electronic products; design tools have been provided to 455 organisations including 350 academic institutions and 105 startups, DLI companies have achieved 35 tape-outs and raised over US$100 million, and the Chips to Startup programme has produced 245 tape-outs from 71 academic institutions; Semicon 2.0 was approved in July 2026 with an outlay of ₹1,27,500 crore; VEGA is developed by C-DAC under the Digital India RISC-V programme and SHAKTI by IIT Madras, both using the open-source royalty-free RISC-V instruction set architecture; tape-out is the despatch of a design to the foundry, first-pass silicon success means the chip works without a redesign, and the business models are fabless, foundry and IDM; semiconductors have conductivity between conductors and insulators, are doped with pentavalent elements for n-type and trivalent for p-type, and unlike metals their conductivity rises with temperature.

Why it matters

• Design is where India can win now. Fabrication takes billions and years; design takes engineers and tools. India has the engineers, and the DLI and C2S numbers show the pipeline being built deliberately.
• First-pass silicon success is the credible signal. Anyone can announce a design. A chip that works on the first attempt says the verification methodology and engineering discipline are genuinely world-class.
• RISC-V removes a permission dependency. Building the national processor programme on an open ISA is a strategic choice, not merely a cost-saving one.
• The honest caveat. VIHAAN is a prototype heading for production tape-out in 2027, not a product on shelves. India still lacks leading-edge fabrication, and equipment, materials and advanced packaging remain import-dependent. The ecosystem is real and improving; it is not yet self-sufficient — and a candidate who says exactly that sounds credible rather than promotional.

Exam relevance in one paragraph

For NDA General Ability, retain: on 15 August 2026 the Ministry of Electronics and Information Technology announced that Aheesa Digital Innovations, a fabless semiconductor startup headquartered in Chennai and supported under the Design Linked Incentive Scheme, had achieved first-pass silicon success with VIHAAN, a networking System-on-Chip purpose-built for fibre broadband and constructed using the indigenous VEGA microprocessor, the chip having been taped out on Republic Day and validated on Independence Day, with production tape-out targeted for 2027 and about forty crore rupees raised from the Tamil Nadu Infrastructure Fund Management Corporation and other investors; semiconductor chip design contributes up to fifty per cent of value addition across the semiconductor value chain and accounts for roughly fifteen to thirty-five per cent of the bill of materials cost of electronic products, and under government programmes chip design tools have been made available to four hundred and fifty-five organisations including three hundred and fifty academic institutions and one hundred and five startups, while companies supported under the Design Linked Incentive Scheme have achieved thirty-five design tape-outs and raised more than one hundred million United States dollars in venture funding, and the Chips to Startup programme has produced two hundred and forty-five chip designs taped out by seventy-one academic institutions; Semicon 2.0 was approved in July 2026 with an outlay of one lakh twenty-seven thousand five hundred crore rupees to build a globally competitive ecosystem spanning design, manufacturing, advanced packaging, equipment, materials, research and skilled manpower; the VEGA processor is developed by the Centre for Development of Advanced Computing under the Digital India RISC-V programme while the SHAKTI family is developed at IIT Madras, both implementing the open-source and royalty-free RISC-V instruction set architecture, which removes dependence on proprietary licensed architectures; and in technical terms a tape-out is the despatch of a completed design to a foundry, first-pass silicon success means the fabricated chip functions correctly without a redesign cycle, a System-on-Chip integrates processor, memory, interfaces and accelerators on one die, and the industry's three business models are fabless design houses, pure-play foundries and integrated device manufacturers.

🎯 Practice MCQs

Q1. VIHAAN, announced in August 2026, is a chip designed for: (a) fibre broadband networking (b) satellite propulsion (c) battery management (d) medical imaging → (a) — a networking System-on-Chip.

Q2. VIHAAN is built using which indigenous microprocessor? (a) VEGA (b) SHAKTI (c) AJIT (d) PARAM → (a) — PARAM is a supercomputer series.

Q3. The VEGA processor is developed by: (a) C-DAC (b) IIT Madras (c) ISRO (d) DRDO → (a) — SHAKTI is IIT Madras.

Q4. VEGA and SHAKTI are based on which instruction set architecture? (a) RISC-V (b) x86 (c) ARM (d) MIPS → (a) — open-source and royalty-free.

Q5. A "fabless" semiconductor company: (a) designs chips but does not manufacture them (b) manufactures chips designed by others (c) does both (d) only tests chips → (a).

Q6. "Tape-out" refers to: (a) sending a completed design to the foundry for manufacture (b) packaging the finished chip (c) testing in the field (d) recycling old chips → (a).

Q7. "First-pass silicon success" means the chip: (a) works as intended on the first fabrication (b) is the first chip made in India (c) uses the smallest node (d) passed a safety audit → (a).

Q8. Adding a pentavalent impurity to silicon produces: (a) n-type semiconductor (b) p-type semiconductor (c) an insulator (d) a superconductor → (a) — trivalent doping gives p-type.

Q9. Unlike a metallic conductor, the conductivity of a semiconductor with rising temperature: (a) increases (b) decreases (c) stays constant (d) becomes zero → (a).

Q10. A System-on-Chip integrates: (a) processor, memory, interfaces and accelerators on one chip (b) only memory (c) only power supplies (d) only sensors → (a).

Q11. Moore's Law is best described as: (a) an empirical observation about transistor density doubling (b) a law of thermodynamics (c) a semiconductor doping rule (d) a networking protocol → (a).

Q12. Semicon 2.0, approved in July 2026, has an outlay of: (a) ₹1,27,500 crore (b) ₹76,000 crore (c) ₹10,000 crore (d) ₹5,000 crore → (a).

Q13. Under the Chips to Startup programme, tape-outs were achieved by: (a) 71 academic institutions (b) 105 startups (c) 350 companies (d) 12 IITs only → (a) — 245 designs.

Q14. The chief strategic advantage of RISC-V is that it is: (a) open-source and royalty-free (b) the fastest architecture (c) proprietary to India (d) the smallest in size → (a).

Q15. A smaller process node (for example 12nm compared with 28nm) generally gives: (a) more transistors, faster switching and lower power per operation (b) larger chips (c) higher power consumption (d) fewer transistors → (a).

📋 How this gets asked (PYQ pattern)

Semiconductors are now a regular NDA science-and-technology area, asked in four ways. The materials item — what a semiconductor is, n-type versus p-type doping, and the temperature behaviour that distinguishes semiconductors from metals; this is classic physics and appears most often. The indigenous-processor item — VEGA with C-DAC and SHAKTI with IIT Madras, and RISC-V as an open ISA; swapping VEGA and SHAKTI is the standard distractor. The terminology item — fabless, foundry, IDM, tape-out and first-pass silicon success. The scheme item — DLI, Chips to Startup and Semicon 2.0 with its ₹1,27,500 crore outlay. The fresh 2026 hook is VIHAAN's first-pass silicon success and the DLI and C2S numbers. We reference the pattern, not any exact past question.

Preparing for NDA? Semiconductors and technological self-reliance are frequent lecturette and GD topics, and being able to explain doping and a tape-out in plain language is exactly the clarity a board rewards. Follow our daily NDA current affairs and train with our faculty in the upcoming Cavalier courses in Delhi.

✍️ Written by Aditya Tiwari — Science, technology & current-affairs faculty at The Cavalier. Reviewed by the Cavalier Faculty Desk. The Cavalier, founded by ex-Army officers, has trained NDA/CDS/SSB aspirants since 2001 (Facebook · YouTube).

Source: PIB / Ministry of Electronics & IT, 15 August 2026. Facts cross-verified with independent sources.