On 31 August 2026, Union Minister for Electronics and Information Technology Shri Ashwini Vaishnaw announced that notifications for all six pillars of the Semicon 2.0 Scheme had been issued. The scheme builds on the first Semicon India Programme, extending fiscal and infrastructure support across the semiconductor value chain — design, fabrication, packaging, equipment, materials, research and talent.
Three claims from the announcement are worth carrying: India has developed 85,000 semiconductor engineers in four years against a ten-year target; the Minister expects close to 10 per cent of the global semiconductor market to be in India in coming years; and students from Tier-II and Tier-III cities have designed more than 250 chips.
The value chain, which everything else depends on
Semiconductor policy is impossible to discuss without the stages, and they are the most examinable content here.
| Stage | What happens | Common name |
|---|---|---|
| Design | The circuit is designed — IP blocks, chips, System-on-Chips (SoCs), modules | "Fabless" if a firm only designs |
| Fabrication | Circuits are etched onto silicon wafers in a fab | Front end |
| ATMP / OSAT | Wafers are cut, chips assembled into packages, tested and marked | Back end |
Why the split matters economically. A fab is among the most capital-intensive facilities in any industry — multi-billion-dollar investments, extreme cleanliness requirements, ultrapure water and uninterrupted power. ATMP/OSAT is far less capital-intensive, more labour-using, and therefore the natural entry point for a country building the sector from a low base. A country generally enters at the back end and works forward. Recognising that ordering is what turns a list of pillars into an argument.
India's historic position is unusual and worth stating: it has long been strong in design — a substantial share of the world's chip design engineering has been done in India for decades — while having almost no fabrication. The country was, in effect, at both ends of the value chain except the middle. Semicon's purpose is to fill it.
The six pillars
| Pillar | Covers |
|---|---|
| 1 — Design | Semiconductor IPs, chips, SoCs and modules for national importance and strategic priorities; the same for the commercial sector; and a Deployment-Linked Incentive (DLI) for IPs/chips/SoCs |
| 2 — Machines and Materials | The semiconductor manufacturing ecosystem — equipment and materials |
| 3 — Setting up more Fabs | Silicon wafer fabs; compound semiconductors / photonics / sensors (including MEMS) and discrete semiconductor fabs; display fabs |
| 4 — ATMP/OSAT | Assembly, Testing, Marking and Packaging facilities |
| 5 — Research and Development | Advanced semiconductor technologies |
| 6 — Talent Development | Skilled workforce |
Two design details are worth noticing.
Pillar 1 separates strategic from commercial design. Chips for "national importance and strategic priorities" are funded distinctly from commercial chips — an acknowledgement that some semiconductor requirements are defence and critical-infrastructure needs where supply security matters more than commercial return.
Pillar 2 is the least obvious and arguably the most important. A country can build fabs and remain dependent, because the equipment and materials that go into a fab — lithography systems, ultrapure chemicals, specialty gases, photoresists, wafer substrates — are themselves supplied by a small number of firms worldwide. A fab you cannot equip or supply is not sovereign capability. Funding the ecosystem rather than only the plant is a more sophisticated policy than the first-generation version, and saying so demonstrates understanding of the supply chain rather than the headline.
Pillar 3's inclusion of compound semiconductors also deserves a line. Silicon dominates logic and memory, but compound semiconductors — gallium nitride, silicon carbide — are superior for power electronics, radio frequency and high-temperature applications, which makes them disproportionately important for electric vehicles, telecom and defence. A country entering late may find more room at the compound end than in competing on leading-edge silicon.
Why the talent number is the one to remember
Of the three claims in the announcement, 85,000 semiconductor engineers trained in four years against a ten-year target is the most meaningful, and here is why.
A fab can be bought; a workforce cannot. Equipment is purchasable with capital. The engineers who design chips, run process lines, and debug yield problems take years to train and longer to become genuinely expert. Talent is the binding constraint on semiconductor capability in most countries that have tried to build it, and every serious national programme has eventually run into it.
The 250 chips designed by students from Tier-II and Tier-III cities is a related and genuinely interesting data point, because it indicates the design capability is not confined to a few metropolitan institutions. Semiconductor design is unusually democratisable — it needs skilled people and expensive software, not a billion-dollar plant — which is why design is where a country with India's engineering base can move fastest.
The honest reading, which belongs in a complete answer: the expectation of "close to 10 per cent of the global semiconductor market" is an aspiration, not a projection with a date attached. India is entering an industry with entrenched incumbents — Taiwan, South Korea, the United States, Japan, China, the Netherlands at specific chokepoints — and where leading-edge fabrication involves technology and yield learning accumulated over decades. Progress at the back end and in design is real and measurable; leading-edge fabrication is a much longer project. Saying both halves is accurate rather than sceptical, and it connects to the wider study of industrial policy and market structures and international trade.
🔑 Revision block
The event. 31 August 2026 — notifications issued for all six pillars of Semicon 2.0, announced by MeitY Minister Ashwini Vaishnaw. Builds on the first Semicon India Programme; six pillars covering 10 categories.
Three claims. 85,000 semiconductor engineers developed in four years against a ten-year target · expectation of close to 10% of the global semiconductor market in India in coming years · students from Tier-II and Tier-III cities have designed more than 250 chips.
The value chain. Design (IPs, chips, SoCs, modules — a design-only firm is fabless) → Fabrication in a fab on silicon wafers (front end) → ATMP/OSAT — Assembly, Testing, Marking and Packaging / Outsourced Semiconductor Assembly and Test (back end).
Why the split matters. A fab is extraordinarily capital-intensive — cleanrooms, ultrapure water, uninterrupted power. ATMP/OSAT is less capital-intensive and more labour-using, so countries typically enter at the back end and work forward.
India's unusual position. Long strong in design, with almost no fabrication — present at both ends of the chain except the middle. Semicon exists to fill it.
The six pillars. 1 Design (strategic/national-importance IPs and SoCs; commercial; Deployment-Linked Incentive) · 2 Machines and Materials · 3 Fabs (silicon wafer; compound semiconductors / photonics / sensors including MEMS; display) · 4 ATMP/OSAT · 5 R&D · 6 Talent Development.
Pillar 2's significance. Fab equipment and materials — lithography systems, ultrapure chemicals, specialty gases, photoresists, wafer substrates — come from a handful of global firms. A fab you cannot equip or supply is not sovereign capability.
Compound semiconductors. Gallium nitride, silicon carbide — better for power electronics, RF and high-temperature use, hence important for EVs, telecom and defence. More room for a late entrant than leading-edge silicon.
The binding constraint. A fab can be bought; a workforce cannot. Talent is the limiting factor in most national semiconductor programmes — which is why the 85,000 figure matters more than any single plant.
The honest limit. The 10% market expectation is an aspiration without a date. Incumbents are entrenched; leading-edge fabrication rests on decades of accumulated yield learning. Back-end and design progress is real; leading-edge fabrication is a much longer project.
🎯 Practice MCQs
Q1. Semicon 2.0 operates through: (a) six pillars covering ten categories (b) three pillars (c) ten pillars covering six categories (d) a single incentive scheme → (a).
Q2. ATMP in the semiconductor value chain stands for: (a) Assembly, Testing, Marking and Packaging (b) Advanced Technology Manufacturing Process (c) Automated Testing and Material Processing (d) Applied Thin-film Metal Patterning → (a).
Q3. A company that designs chips but does not manufacture them is described as: (a) fabless (b) foundry (c) OSAT (d) integrated device manufacturer → (a).
Q4. Which of these is a compound semiconductor material? (a) Gallium nitride (b) Silicon (c) Germanium (d) Copper → (a) — silicon carbide is the other common example.
Q5. India's historic strength in the semiconductor value chain has been in: (a) design (b) fabrication (c) equipment manufacture (d) raw wafer production → (a).
Q6. The number of semiconductor engineers India has developed, per the announcement, is: (a) 85,000 (b) 250 (c) 10,000 (d) 1 lakh → (a) — in four years against a ten-year target.
Q7. Semicon 2.0 falls under which ministry? (a) Electronics and Information Technology (b) Commerce and Industry (c) Science and Technology (d) Heavy Industries → (a).
Q8. MEMS, referred to under the fabs pillar, stands for: (a) Micro-Electro-Mechanical Systems (b) Metal Etched Micro Structures (c) Modular Electronic Manufacturing Standards (d) Multi-layer Embedded Memory Systems → (a).
Q9. Compound semiconductors are particularly suited to: (a) power electronics, RF and high-temperature applications (b) memory storage only (c) display panels only (d) photovoltaic cells only → (a).
Q10. The pillar addressing equipment and materials is significant because: (a) a fab cannot operate without equipment and materials from a narrow global supplier base (b) equipment is cheap (c) materials are locally abundant (d) fabs do not need chemicals → (a).
Q11. In the semiconductor value chain, the 'front end' refers to: (a) wafer fabrication (b) assembly and packaging (c) chip design (d) product marketing → (a).
Q12. A Deployment-Linked Incentive under Pillar 1 supports: (a) semiconductor IPs, chips and SoCs for deployment (b) fab construction (c) worker training (d) raw material imports → (a).
📋 How this gets asked (PYQ pattern)
Industrial-policy questions on semiconductors come in four shapes. The acronym item — ATMP, OSAT, SoC, MEMS and fabless, asked as straight recall. The value-chain item — ordering design, fabrication and packaging, or identifying which stage is most capital-intensive. The material item — silicon against compound semiconductors, and what each suits, a chemistry question inside an economics topic. The ministry item — MeitY for Semicon, set against Commerce and Industry for PLI schemes generally and Heavy Industries for automotive.
The fresh 2026 hook is the six pillars and ten categories, and the 85,000 engineers figure. A statement pair on the pillar structure and the meaning of ATMP/OSAT is the likeliest single item — both halves true. As always, we describe the recurring pattern, not any exact past question.
Preparing for CDS or OTA? Semiconductors are the current standard example of supply-chain strategy, and the value-chain sequence is what makes an essay answer concrete rather than generic. Build the base with our notes on market structures and international trade, follow the daily CDS/OTA current affairs, and prepare with our faculty in the upcoming Cavalier courses in Delhi.
✍️ Written by Hitendra Deswal — Economy & industrial-policy faculty at The Cavalier. Reviewed by the Cavalier Faculty Desk. The Cavalier, founded by ex-Army officers, has trained NDA/CDS/SSB aspirants since 2001 (Facebook · YouTube).
Source: PIB / Ministry of Electronics & IT, 31 August 2026. Value-chain and scheme details cross-verified with independent sources.